Current sensing circuit and current sensing assembly including the same

ABSTRACT

A current sensing circuit for use with a Rogowski coil arranged around a conductor having a primary current includes input terminals structured to receive an output voltage of the Rogowski coil, an analog to digital converter structured to convert a differential voltage to a digital differential voltage signal, a digital integrator structured to receive the digital differential voltage signal, to implement a discrete-time transfer function that is a transform of a transfer function of an analog integrator, and to output a digital integrator output signal, and a direct current blocker filter structured to remove a direct current bias from the digital integrator output signal and to output a digital current output signal that is proportional to the primary current in the conductor.

BACKGROUND Field

The disclosed concept relates generally to circuits, and in particular, to a current sensing circuit for resolving current from the output of a Rogowski coil.

Background Information

Accurate measurement of electrical current is important to numerous protection, metering, and control applications. Among numerous electrical current measurement technologies, Rogowski coil based current sensing technology has been widely used to measure alternating current (AC) or high speed current pulses in protection, metering, and monitoring applications.

FIG. 1 is an isometric view of a Rogowski coil 2. The Rogowski coil 2 includes coils wound over a non-magnetic core. As a result, the Rogowski coil does not saturate and offers a wide operating current range. The Rogowski coil 2 is arranged for use in sensing a current i_(P)(t) flowing through a conductor 8. The output of the Rogowski coil 2 is a voltage v_(R)(t) between its output terminals 4,6.

FIG. 2 is a circuit diagram of current sensing circuitry used with the Rogowski coil 2 of FIG. 1. The current sensing circuitry includes terminals 10,12 that connect to the output terminals 4,6 of the Rogowski coil 2 of FIG. 1. The voltage v_(R)(t) is realized between the terminals 10,12. Ferrite beads 14,16 are electrically connected to the terminals 10,12 and suppress high frequency noise in the voltage v_(R)(t). Outputs of the ferrite beads 14,16 are electrically connected to a resistor-capacitor-resistor shunt path including two resistors 18,20 and a capacitor 22. The two resistors 18,20 and the capacitor 22 constitute an RC-filter that acts as an analog integrator. An instrumentation amplifier 24 is electrically connected across the capacitor 22. The output voltage v_(o)(t) of the instrumentation amplifier 24 is proportional to the current i_(P)(t) flowing through the conductor 8.

There are some challenges with using the current sensing circuitry of FIG. 2 to resolve the current i_(P)(t) flowing through the conductor 8 of FIG. 1. First, it is difficult to resolve the current i_(P)(t) from the relatively small output voltage v_(R)(t) of the Rogowski coil 2. Second, it is difficult to cope with large temperature variations, which frequently occur in circuit breaker operation.

As previously noted, the Rogowski coil 2 includes a non-magnetic core. Due to the non-magnetic core, the mutual coupling between the Rogowski coil 2 and the conductor 8 is small compared to the mutual coupling between a conductor and a current sensing element with a magnetic core such as a current transformer. This results in a small output voltage v_(R)(t) for the Rogowski coil 2. Moreover, the use of an analog integrator, as is used in the current sensing circuitry of FIG. 2, aggravates the situation. Compared to the output voltage v_(R)(t) of the Rogowski coil 2, the output voltage v_(o)(t) of the instrumentation amplifier 24 is even smaller. Small voltages have smaller signal to noise ratios (SNR) than larger voltages. Therefore, the small voltages are more susceptible to noise and can cause difficulties when high precision is needed, such as in metering and control applications.

Table 1 shows a relationship between operating temperature and coil resistance for a Rogowski coil, such as the Rogowski coil 2 of FIG. 1.

TABLE 1 Operating Temperature (° C.) Coil Resistance (Ω) 24.4 102.08 40 108.55 60 116.52 80 124.25 100 131.92 120 139.63 140 147.56 160 155.30 180 162.83

As shown in Table 1, variations in temperature cause changes in the coil resistance of a Rogowski coil. If the current sensing circuitry of FIG. 2 is integrated with the Rogowski coil, properties of components of the current sensing circuitry of FIG. 2, such as resistances of the two resistors 18,20, can also change due to variations in temperature. The variations in properties of the current sensing circuitry can make it difficult to accurately measure current. The temperature inside some circuit breakers can reach 160° C., so it is difficult to use the current sensing circuitry of FIG. 2 to accurately measure current in such an application.

There is room for improvement in current sensing circuitry.

SUMMARY

These needs and others are met by embodiments of the disclosed concept in which a current sensing circuit includes a digital integrator.

In accordance with one aspect of the disclosed concept, a current sensing circuit for use with a Rogowski coil arranged around a conductor having a primary current comprises: input terminals structured to receive an output voltage of the Rogowski coil; filtering elements structured to filter high frequency voltage from the output voltage and to output a filtered output voltage; an amplifier structured to receive the filtered output voltage and produce a differential voltage; an analog to digital converter structured to convert the differential voltage to a digital differential voltage signal; a digital integrator structured to receive the digital differential voltage signal, to implement a discrete-time transfer function that is a transform of a transfer function of an analog integrator, and to output a digital integrator output signal; a direct current blocker filter structured to remove a direct current bias from the digital integrator output signal and to output a digital current output signal that is proportional to the primary current in the conductor.

In accordance with another aspect of the disclosed concept, a method of implementing a digital integrator comprises providing a sampling frequency f_(s); providing a rated supply frequency f_(e); providing a phase difference number of samples Δn; obtaining a power grid's normalized angular frequency at rated condition using the following equation:

$\omega_{e} = {2\; \pi \frac{f_{e}}{f_{S}}}$

obtaining a first coefficient a₁ based on the following equation:

$a_{1} = \frac{\cos \left( {\Delta \; {n \cdot \omega_{e}}} \right)}{\cos \left\lbrack {\left( {{\Delta \; n} - 1} \right) \cdot \omega_{e}} \right\rbrack}$

obtaining a second coefficient based on the following equation:

b ₀=√{square root over (1−2a ₁ cos ω_(e) +a ₁ ²)}

implementing the digital integrator as a digital filter using the first coefficient a₁ and the second coefficient b₀.

In accordance with another aspect of the disclosed concept, a method of implementing a digital integrator comprises: providing a sampling frequency f_(s); providing a rated supply frequency f_(e); providing a phase difference number of samples Δn; obtaining a power grid's normalized angular frequency at rated condition using the following equation:

$\omega_{e} = {2\; \pi \frac{f_{e}}{f_{S}}}$

obtaining a first coefficient a₁ based on the following equation:

$a_{1} = \frac{\cos \left\lbrack {\left( {{\Delta \; n} + \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}{\cos \left\lbrack {\left( {{\Delta \; n} - \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}$

obtaining a second coefficient b₀ and a third coefficient b₁ based on the following equation:

$b_{0} = {b_{1} = \sqrt{\frac{1 - {2\; a_{1}\cos \mspace{11mu} \omega_{e}} + a_{1}^{2}}{2 \cdot \left( {1 + {\cos \mspace{11mu} \omega_{e}}} \right)}}}$

implementing the digital integrator as a digital filter using the first coefficient a₁, the second coefficient b₀, and the third coefficient b₁.

BRIEF DESCRIPTION OF THE DRAWINGS

A full understanding of the disclosed concept can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:

FIG. 1 is an isometric view of a Rogowski coil;

FIG. 2 is a circuit diagram of a current sensing circuit used with the Rogowski coil of FIG. 1;

FIG. 3 is a circuit diagram of a current sensing circuit in accordance with an example embodiment of the disclosed concept;

FIG. 4 is a graph of waveforms of a primary current, an output voltage of a Rogowski coil, and a primary current signal;

FIG. 5 is a flowchart of a method of determining coefficients of a digital integrator in accordance with an example embodiment of the disclosed concept;

FIG. 6 is a flowchart of another method of determining coefficients of a digital integrator in accordance with an example embodiment of the disclosed concept;

FIG. 7a is a signal flow graph of a digital biquadratic filter in accordance with an example embodiment of the disclosed concept;

FIGS. 7b and 7c are signal flow graphs of digital integrators implemented in a digital biquadratic filter in accordance with example embodiments of the disclosed concept; and

FIG. 7d is a signal flow graph of a DC blocker filter implemented in a digital biquadratic filter in accordance with an example embodiment of the disclosed concept.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Directional phrases used herein, such as, for example, left, right, front, back, top, bottom and derivatives thereof, relate to the orientation of the elements shown in the drawings and are not limiting upon the claims unless expressly recited therein.

As employed herein, the term “processor” shall mean a programmable analog and/or digital device that can store, retrieve, and process data; a computer; a workstation; a personal computer; a microprocessor; a microcontroller; a microcomputer; a central processing unit; a mainframe computer; a mini-computer; a server; a networked processor; or any suitable processing device or apparatus.

As employed herein, the statement that two or more parts are “coupled” together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

FIG. 3 is a circuit diagram of current sensing circuitry 100 in accordance with an example embodiment of the disclosed concept. The current sensing circuitry 100 is structured to receive as input the output voltage of a Rogowski coil such as, for example and without limitation, the output voltage v_(R)(t) of the Rogowski coil 2 of FIG. 1. The current sensing circuitry 100 includes first and second input terminals 102,104. The first and second input terminals 102,104 may be electrically connected to output terminals of a Rogowski coil such as the output terminals 4,6, of the Rogowski coil 2 of FIG. 1. Together, the current sensing circuitry 100 and the Rogowski coil 2 form a current sensing assembly.

The current sensing circuitry 100 further includes first and second filters 106,108. The first and second filter 106,108 are respectively electrically connected to the first and second input terminals 102,104. In some example embodiments of the disclosed concept, the first and second filters 106,108 are filters structured to filter out high frequency voltage received through the first and second input terminals 102,104. In some example embodiments of the disclosed concept, the first and second filters 106,108 are ferrite beads. However, it will be appreciated by those having ordinary skill in the art that other types of filters may be employed as the first and second filters 106,108 without departing from the scope of the disclosed concept.

Outputs of the first and second filters 106,108 are electrically connected to an amplifier 110. The amplifier 110 is structured to produce a differential voltage v′_(R)(t) from the output of the first and second filters 106,108. The differential voltage v′_(R)(t) is a floating voltage that is the difference between the outputs of the first and second filters 106,108. The output of the amplifier 110 is electrically connected to an analog to digital converter (ADC) 112. The ADC 112 is structured to convert the differential voltage v′_(R)(t) into a digital differential voltage signal v_(R)[n] in a discrete-time domain.

The output of the ADC 112 is provided to a digital integrator 114 and the ADC 112 is structured to provide the digital differential voltage signal v_(R)[n] to the digital integrator 114. The digital integrator 116 is structured to integrate the digital differential voltage signal v_(R)[n] to produce a digital integrator output signal v_(D)[n].

In some example embodiments of the disclosed concept, the digital integrator 114 implements a transfer function that is a discrete-time transform of the transfer function of an analog integrator. For example and without limitation, the digital integrator 114 may implement a discrete-time transform of the transfer function of the analog integrator formed by the resistors 18,20 and capacitor 22 of the current sensing circuit of FIG. 2. For example, the transfer function of the analog integrator of FIG. 2 in the s-domain is shown in Equation 1:

$\begin{matrix} {{H(s)} = {\frac{V_{o}(s)}{V_{R}(s)} = {\frac{1}{1 + {sCR}} = {\frac{\frac{1}{RC}}{s + \frac{1}{RC}} = \frac{\alpha}{s + \alpha}}}}} & \left( {{Eq}.\mspace{14mu} 1} \right) \end{matrix}$

In Equation 1, H(s) is the transfer function of the analog integrator in the s-domain, V_(o)(s) is the output of the instrumentation amplifier 24 in the s-domain and V_(R)(s) is the output voltage of the Rogowski coil 2 in the s-domain. The capacitor 22 has a capacitance of C and the resistors 18,20 each have a resistance of R/2.

$\alpha = {\frac{1}{RC}.}$

In some example embodiments of the disclosed concept, the digital integrator 114 implements a discrete-time transform of the transfer function of an analog integrator obtained using an impulse-invariant transform. Using the analog integrator of FIG. 2 as an example, the inverse Laplace transform of the analog integrator's transfer function (H(s) shown in Equation 1) is shown in Equation 2.

h _(a)(t)=α·e ^(−αt) ·u(t)   (Eq. 2)

In Equation 2, h_(a)(t) is the analog integrator's transfer function in the continuous-time domain, and u(t) is a unit step function. The discrete-time impulse response h_(d)[n] of the analog integrator is shown in Equation 3. The quantity T_(S) denotes a sampling interval. n denotes a temporal index, i.e., the nth sample in a discrete-time system.

h _(d) [n]=T _(S) ·h _(a)(nT _(S))   (Eq. 3)

Equation 4 shows the result of substituting the analog integrator's transfer function in the continuous-time domain h_(a)(t) into Equation 3.

h _(d) [n]=α·T _(S) ·e ^(−αnT) ^(S) ·u[n]   (Eq. 4)

Applying the z-transform to the discrete-time impulse response h_(d)[n] shown in Equation 4 results in the discrete-time transfer function H(z) shown in Equation 5.

$\begin{matrix} {{H(z)} = {\frac{y(z)}{x(z)} = {\frac{\alpha \cdot T_{S}}{1 - {e^{{- \alpha}\; T_{S}}z^{- 1}}} = \frac{b_{0}}{1 - {a_{1}z^{- 1}}}}}} & \left( {{Eq}.\mspace{14mu} 5} \right) \end{matrix}$

In Equation 5, x(z) and y(z) are the digital integrator's 114 input and output, respectively. In Equation 5,

$a_{1} = {e^{{- a}\; T_{S}} = e^{- \frac{T_{S}}{RC}}}$

and b₀=α·T_(s)·z⁻¹ denotes a one-sample delay. The discrete-time transfer function H(z) shown in Equation 5 is a discrete-time transformation of the transfer function of the analog integrator of FIG. 2 obtained using an impulse-invariant transform. In some example embodiments of the disclosed concept, the digital integrator 114 implements the discrete-time transfer function H(z) shown in Equation 5.

In some example embodiments of the disclosed concept, the digital integrator 114 implements a discrete-time transform of the transfer function of an analog integrator obtained using a bilinear transform. Equation 6 is a discrete-time approximation.

$\begin{matrix} {\frac{2}{T_{S}} \cdot \frac{1 - z^{- 1}}{1 + z^{- 1}}} & \left( {{Eq}.\mspace{14mu} 6} \right) \end{matrix}$

Substituting s in Equation 1 with the discrete-time approximation shown in Equation 6 results in the discrete-time transfer function H(z) shown in Equation 7.

$\begin{matrix} {{H(z)} = {\frac{y(z)}{x(z)} = {\frac{\frac{\alpha \; T_{S}}{2 + {\alpha \; T_{S}}} + {\frac{\alpha \; T_{S}}{2 + {\alpha \; T_{S}}}z^{- 1}}}{1 - {\frac{2 - {\alpha \; T_{S}}}{2 + {\alpha \; T_{S}}}z^{- 1}}} = \frac{b_{0} + {b_{1}z^{- 1}}}{1 - {a_{1}z^{- 1}}}}}} & \left( {{Eq}.\mspace{14mu} 7} \right) \end{matrix}$

In Equation 7,

$a_{1} = {{\frac{2 - {\alpha \; T_{S}}}{2 + {\alpha \; T_{S}}}\mspace{14mu} {and}\mspace{14mu} b_{0}} = {b_{1} = {\frac{\alpha \; T_{S}}{2 + {\alpha \; T_{S}}}.}}}$

The discrete-time transfer function H(z) shown in Equation 7 is a discrete-time transformation of the transfer function of the analog integrator of FIG. 2 obtained using a bilinear transform. In some example embodiments of the disclosed concept, the digital integrator 114 implements the discrete-time transfer function H(z) shown in Equation 7.

According to Equation 5, the digital integrator 114 has coefficients a₁ and b₀. In some example embodiments of the disclosed concept, the coefficients a₁ and b₀ are set based on the digital integrator's 114 phase delay.

In an example embodiment of the disclosed concept, the coefficients a₁ and b₀ of the digital integrator 114 implements a discrete-time transfer function that is an impulse-invariant transform of the transfer function of an analog integrator (e.g., without limitation, the discrete-time transfer function H(z) shown in Equation 5) and the coefficients a₁ and b₀ a set based on the phase delay of the digital integrator 114.

To compute the coefficients a₁ and b₀ in this example embodiment, it is useful to first compute the amplitude and phase response of the digital integrator 114. Equation 8 is the frequency response of the discrete-time transfer function H(z) of Equation 5 when z is replaced with e^(jω).

$\begin{matrix} {{H\left( e^{j\; \omega} \right)} = {\frac{b_{0}}{1 - {a_{1}e^{{- j}\; \omega}}} = \frac{b_{0} \cdot \left( {1 - {a_{1}\; \cos \; \omega} - {{j \cdot a_{1}}\; \sin \; \omega}} \right)}{1 - {2a_{1}\; \cos \; \omega} + a_{1}^{2}}}} & \left( {{Eq}.\mspace{14mu} 8} \right) \end{matrix}$

From Equation 8, the digital integrator's 114 amplitude response A(ω) and phase response φ(ω) may be obtained. The amplitude response A(ω) is shown in Equation 9 and the phase response φ(ω) is shown in Equation 10.

$\begin{matrix} {{A(\omega)} = {{{H\left( e^{j\; \omega} \right)}} = \frac{b_{0}}{\sqrt{1 - {2a_{1}\; \cos \; \omega} + a_{1}^{2}}}}} & \left( {{Eq}.\mspace{14mu} 9} \right) \\ {{\phi (\omega)} = {{\angle \; {H\left( e^{j\; \omega} \right)}} = {a\; {\tan \left( \frac{{{- a_{1}} \cdot \sin}\mspace{11mu} \omega}{1 - {a_{1}\; \cos \; \omega}} \right)}}}} & \left( {{Eq}.\mspace{14mu} 10} \right) \end{matrix}$

The primary current i_(p)(t) through the conductor 8 (FIG. 1) is shown in Equation 11.

i _(P)(t)=A _(P)·sin(2πf _(e) t)=A _(P)·cos(2πf _(e) t+φ _(P))   (Eq. 11)

In Equation 11, A_(p) is the primary current's amplitude, f_(e) (in hertz) is the rated supply frequency, and the phase shift φ_(p)=−π/2. For a power grid with a rated supply frequency of 60 Hz, f_(e)=60 Hz. Given the primary current i_(p)(t) shown in Equation 11, the output voltage v_(R)(t) of the Rogowski coil 2 is shown in Equation 12.

$\begin{matrix} {{v_{R}(t)} = {{{M_{R} \cdot \frac{d}{dt}}{i_{P}(t)}} = {2\; \pi \; M_{R}A_{P}f_{e}\; {\cos \left( {2\; \pi \; f_{e}t} \right)}}}} & \left( {{Eq}.\mspace{14mu} 12} \right) \end{matrix}$

In Equation 12,

$M_{R} = {{{- \frac{\mu_{0}{Nh}_{0}}{2\; \pi}} \cdot \ln}\frac{r_{2}}{r_{1}}}$

where μ₀ is the permeability of the Rogowski coil 2, N is the number of turns of the Rogowski coil 2, h₀ is the height of the Rogowski coil 2, r₂ is an outer radius of the Rogowski coil 2, and r₁ is an inner radius of the Rogowski coil 2 (shown in FIG. 1).

Equation 13 shows the output voltage of the Rogowski coil 2 in the discrete-time domain.

v _(R) [n]=2πM _(R) A _(P) f _(e) cos(2πf _(e) ·nT _(S))=2πM _(R) A _(P) f _(e) cos(ω_(e) ·n)   (Eq. 13)

In Equation 13,

$\omega_{e} = {2\pi \frac{f_{e}}{f_{s}}}$

is the power grid's normalized angular frequency at rated condition. f_(s) is the sampling frequency (in hertz) of the ADC 112. It is related to the sampling interval via f_(s)=1/T_(S). The digital integrator 114 receives the Rogowski coil's 2 output voltage signal v_(R)[n] as an input and computes a primary current signal y[n]. Given the digital integrator's 114 amplitude and phase responses shown in Equations 9 and 10, the primary current signal y[n] from the digital integrator 114 is shown in Equation 14.

y[n]=2πM _(R) A _(P) f _(e) ·A(ω_(e))·cos [ω_(e) ·n+φ(ω_(e))]   (Eq. 14)

In Equation 14, A(ω_(e)) and φ(ω_(e)) are the digital integrator's 114 amplitude and phase responses at We, respectively. If φ(ω_(e))=−π/2, then the primary current signal y[n] is proportional to cos

$\left( {{\omega_{e}n} - \frac{\pi}{2}} \right) = {{\cos \left( {{\omega_{e}n} + \phi_{p}} \right)}.}$

Equation 15 shows the phase difference (in radians) between φ(ω_(e)) and φ_(p).

$\begin{matrix} {{\Delta\phi} = {{{\phi \left( \omega_{e} \right)} - \phi_{P}} = {{\phi \left( \omega_{e} \right)} + \frac{\pi}{2}}}} & \left( {{Eq}.\mspace{14mu} 15} \right) \end{matrix}$

Note that the phase difference Δφ corresponds to the phase lead between the primary current signal y[n] and the primary current i_(p)(t) in the Rogowski coil 2. FIG. 4 illustrates waveforms of the Rogowski coil's 2 output voltage v_(R)(t), the primary current i_(p)(t), and the primary current signal y[n] and provides a visual illustration of the phase difference Δφ between the primary current signal y[n] and the primary current i_(p)(t).

The phase difference number of samples Δn (i.e., the number of samples between the primary current signal y[n] and the primary current i_(p)(t)) may be determined using Equation 16.

$\begin{matrix} {{\Delta \; n} = {\frac{\Delta \; t}{T_{S}} = {\frac{{\Delta\phi}\text{/}\left( {2\pi \; f_{e}} \right)}{T_{S}} = {\frac{\Delta\phi}{2\pi \frac{f_{e}}{f_{S}}} = \frac{\Delta\phi}{\omega_{e}}}}}} & \left( {{Eq}.\mspace{14mu} 16} \right) \end{matrix}$

Using Equations 10, 15, and 16 it is possible to determine a relation between Δn and the coefficient a₁. The relation is shown in Equation 17.

$\begin{matrix} {a_{1} = \frac{\cos \left( {\Delta \; {n \cdot \omega_{e}}} \right)}{\cos \left\lbrack {\left( {{\Delta \; n} - 1} \right) \cdot \omega_{e}} \right\rbrack}} & \left( {{Eq}.\mspace{14mu} 17} \right) \end{matrix}$

There are different ways to determine the coefficient b₀ once the coefficient a₁ has been determined. For example and without limitation, in some example embodiments of the disclosed concept, the digital integrator 114 has a unity gain at the power grid's normalized angular frequency at rated condition ω_(e). Using Equation 9 and setting the amplitude response A(ω_(e)) of the digital integrator 114 to one at the power grid's normalized angular frequency at rated condition ω_(e), it is possible to derive Equation 18 which shows the relation between the coefficients a₁ and b₀ when the digital integrator 114 has a unity gain at the power grid's normalized angular frequency at rated condition ω_(e).

b ₀=√{square root over (1−2a ₁ cos ω_(e) +a ₁ ²)}   (Eq. 18)

Using Equations 17 and 18, it is possible to input phase difference number of samples Δn, the sampling frequency f_(s), and the rated supply frequency f_(e) to determine the coefficients a₁ and b₀. For example and without limitation, in some example embodiments of the disclosed concept, the phase difference number of samples Δn is 1, the sampling frequency f_(s) is 4800 Hz, and the primary current frequency f_(e) is 60 Hz. The corresponding coefficients a₁ and b₀ are 0.9969 and 0.07846, respectively.

Table 2 shows some values of the coefficients a₁ and b₀ when the sampling frequency f_(s) is 4800 Hz and the primary current frequency f_(e) is 60 Hz.

TABLE 2 Δn a₁ b₀ 1 0.9969 0.07846 2 0.9907 0.07870 3 0.9845 0.07944 4 0.9781 0.08069

FIG. 5 is a flowchart for computing the coefficients a₁ and b₀ based on the sampling frequency f_(s), the rated supply frequency f_(e), and the phase difference number of samples Δn when the digital integrator 114 uses a discrete-time transfer function that is an impulse-invariant transformation of the transfer function of an analog integrator. In some example embodiments of the disclosed concept, the coefficient b₀ may be scaled by a non-zero factor kb to a coefficient b′₀.

First, the sampling frequency f_(s), the rated supply frequency f_(e), and the phase difference number of samples Δn are provided. The power grid's normalized angular frequency at rated condition We is obtained using

$\omega_{e} = {2\pi \frac{f_{e}}{f_{s}}}$

at 200. The first coefficient a₁ is obtained using equation 17 at 202, and the second coefficient b₀ is obtained using equation 18 at 204. In some example embodiments of the disclosed concept, the second coefficient b₀ may be scaled at 206 to obtain a scaled second coefficient b′₀.

In some example embodiments of the disclosed concept, the sampling frequency f_(s) is chosen as a predetermined multiple of the rated supply frequency f_(e). In this case, the coefficients a₁ and b₀ will remain the same even if the rated supply frequency f_(e) is changed.

Equations 8-18 are related to determining the coefficients a₁ and b₀ of the digital integrator 114 when the digital integrator 144 implements a discrete-time transfer function that is an impulse-invariant transformation of the transfer function of an analog integrator. In some example embodiments of the disclosed concept, the digital integrator 114 implements a discrete time transfer function that is a bilinear transformation of the transfer function of an analog integrator. In this case, the following equations may be used to determine the coefficients a₁, b₀, and b₁. In some example embodiments of the disclosed concept, the coefficients b₀ and b₁ are equal.

The discrete-time transfer function H(z) in Equation 7 is the bilinear transformation of the transfer function of an analog integrator. The frequency response of the discrete-time transfer function of Equation 7 is shown in Equation 19.

$\begin{matrix} \begin{matrix} {{H\left( e^{j\; \omega} \right)} =} & {\frac{b_{0}\left( {1 + e^{{- j}\; \omega}} \right)}{1 - {a_{1}e^{{- j}\; \omega}}}} \\ {=} & {{\frac{b_{0}}{1 - {2a_{1}\mspace{14mu} \cos \mspace{14mu} \omega} + a_{1}^{2}} \cdot \left\lbrack {{\left( {1 - a_{1}} \right) \cdot \left( {1 + {\cos \mspace{14mu} \omega}} \right)} - {j \cdot}} \right.}} \\  & \left. {{\left( {1 + a_{1}} \right) \cdot \sin}\mspace{14mu} \omega} \right\rbrack \end{matrix} & \left( {{Eq}.\mspace{14mu} 19} \right) \end{matrix}$

From Equation 19, it is possible to determine the amplitude response and phase response, which are respectively shown in Equations 20 and 21.

$\begin{matrix} {{A(\omega)} = {\left| {H\left( e^{j\; \omega} \right)} \right| = {b_{0} \cdot \sqrt{\frac{2 \cdot \left( {1 + {\cos \mspace{14mu} \omega}} \right)}{1 - {2a_{1}\mspace{14mu} \cos \mspace{14mu} \omega} + a_{1}^{2}}}}}} & \left( {{Eq}.\mspace{14mu} 20} \right) \\ {{\phi (\omega)} = {{\angle \; {H\left( e^{j\; \omega} \right)}} = {{atan}\left\lbrack \frac{{{- \left( {1 + a_{1}} \right)} \cdot \sin}\mspace{14mu} \omega}{\left( {1 - a_{1}} \right) \cdot \left( {1 + {\cos \mspace{14mu} \omega}} \right)} \right\rbrack}}} & \left( {{Eq}.\mspace{14mu} 21} \right) \end{matrix}$

The phase difference Δφ and the phase difference number of samples Δn are provided by Equations 15 and 16, respectively. Using Equations 15, 16, and 21, it is possible to determine the relation between the phase difference number of samples Δn and the coefficient a₁, as is shown in Equation 22.

$\begin{matrix} {a_{1} = \frac{\cos \left\lbrack {\left( {{\Delta \; n} + \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}{\cos \left\lbrack {\left( {{\Delta \; n} - \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}} & \left( {{Eq}.\mspace{14mu} 22} \right) \end{matrix}$

Assuming that the digital integrator 114 has a unity gain at ω_(e), the coefficient b₀ is provided by Equation 23.

$\begin{matrix} {b_{0} = {b_{1} = \sqrt{\frac{1 - {2a_{1}\mspace{14mu} \cos \mspace{14mu} \omega_{e}} + a_{1}^{2}}{2 \cdot \left( {1 + {\cos \mspace{14mu} \omega_{e}}} \right)}}}} & \left( {{Eq}.\mspace{14mu} 23} \right) \end{matrix}$

Table 3 shows some values for coefficients a₁, b₀, and b₁ when the rated supply frequency f_(e) is 50 Hz and the sampling frequency f_(s) is 4000 Hz (e.g., the sampling frequency f_(s) is 80 times the rated supply frequency f_(e)).

TABLE 3 Δn a₁ b₀ b₁ 1 0.9938 0.03929 0.03929 2 0.9876 0.03953 0.03953 3 0.9813 0.04003 0.04003 4 0.9748 0.04079 0.04079

FIG. 6 is a flowchart for computing the coefficients a₁, b₀, and b₁ based on the sampling frequency f_(s), the rated supply frequency f_(e), and the phase difference number of samples Δn when the digital integrator 114 uses a discrete-time transfer function that is a bilinear transformation of the transfer function of an analog integrator. In some example embodiments of the disclosed concept, the coefficients b₀ and b₁ may be scaled by a non-zero factor kb to coefficients b′₀ and b′₁.

First, the sampling frequency f_(s), the rated supply frequency f_(e), and the phase difference number of samples Δn are provided. The power grid's normalized angular frequency at rated condition We is obtained using

$\omega_{e} = {2\pi \frac{f_{e}}{f_{S}}}$

at 210. The first coefficient a₁ is obtained using equation 22 at 212. The second coefficient b₀ and the third coefficient b₁ are obtained using equation 23 at 214 and 216. In some example embodiments of the disclosed concept, the second coefficient b₀ and third coefficient b₁ may be scaled at 218 and 220 to obtain a scaled second coefficient b′₀ and a scaled third coefficient b′₁.

In accordance with example embodiments of the disclosed concept, the phase delay (e.g., the phase difference number of sample Δn) of the digital integrator 114 may be precisely designed and tuned. The design and tuning affords more precise control of the phase delay than analog integrators such as the one used in the current sensing circuitry shown in FIG. 2. The ability to tune the digital integrator's 114 phase delay significantly simplifies metering calibration tasks and helps meet performance constraints in protection, metering, and monitoring applications.

Referring back to FIG. 3, current sensing circuitry 100 further includes a DC blocker filter 116. The DC blocker filter 116 is structured to receive the output of the digital integrator 114. The DC blocker filter 116 is structured to filter the output of the digital integrator to remove a DC bias from the output of the digital integrator 114. The DC blocker filter 116 produces a digital current output signal i_(Q)[n]. The digital current output signal i_(Q)[n] is proportional to the primary current i_(p)(t).

In some example embodiments of the disclosed concept, the DC blocker filter 116 implements the transfer function shown in Equation 24.

$\begin{matrix} {{H(z)} = {\frac{y(z)}{x(z)} = \frac{{b\;}_{0} + {b_{1}z^{- 1}}}{1 - {a_{1}z^{- 1}}}}} & \left( {{Eq}.\mspace{14mu} 24} \right) \end{matrix}$

In Equation 24, 0<a₁<1, b₀=1, and b₁=−1. In some example embodiments of the disclosed concept, the value of a₁ is chosen to be close to 1 to provide reasonably good DC blocking performance.

In some example embodiments of the disclosed concept, the digital integrator 114 and the DC blocker filter 116 may be implemented as digital biquadratic filters, also referred to as a digital biquad filter. In some example embodiments of the disclosed concept, the digital biquad filter has the transfer function shown in Equation 25.

$\begin{matrix} {{H(z)} = {\frac{y(z)}{x(z)} = \frac{b_{0} + {b_{1}z^{- 1}} + {b_{2}z^{- 2}}}{1 - {a_{1}z^{- 1}} - {a_{2}z^{- 2}}}}} & \left( {{Eq}.\mspace{14mu} 25} \right) \end{matrix}$

Table 4 shows the selection of coefficients a₁, a₂, b₀, b₁, and b₂ based on the type of component that is implemented in the digital biquad filter.

TABLE 4 Type a₁ a₂ b₀ b₁ b₂ Digital Impulse-invariant transform ≠0 =0 ≠0 =0 =0 Integrator Bilinear transform ≠0 =0 ≠0 =b₀ =0 DC blocker filter ≠0 =0 =1 =−1 =0

FIG. 7a is a signal flow graph of a digital biquad filter in the discrete-time domain. In FIG. 7a , x[n] is the input to the digital biquad filter and y[n] is the output of the digital biquad filter. Applying the coefficient values in Table 4 to the signal flow graph of FIG. 7a produces signal flow graphs corresponding to the different types of filters that maybe implemented in the digital biquad filter. FIG. 7b is a signal flow graph of a digital integrator using the impulse-invariant transform. FIG. 7c is a signal flow graph of a digital integrator using a bilinear transform, and FIG. 7d is a signal flow graph of a DC blocker filter.

In some example embodiments of the disclosed concept, the digital integrator output signal v_(D)[n] of the digital integrator 114 may be used for the purpose of circuit protection and the digital current output signal i_(Q)[n] is proportional to the primary current i_(p)(t) and may be used for metering or control purposes. However, it will be appreciated by those having ordinary skill in the art that the outputs v_(D)[n] and i_(Q)[n] may be used for any purpose without departing from the scope of the disclosed concept.

The ADC 112 may be implemented using any suitable electronic components such as, for example and without limitation, an integrated circuit and/or other circuit components. The digital integrator 114 and the DC blocker filter 116 may be implemented using any suitable electronic components such as, for example and without limitation, microchips, other circuit components, and/or electronic components used in digital filtering applications. One or more of the ADC 112, the digital integrator 114, and the DC blocker filter 116 may be implemented using any suitable components. For example and without limitation, one or more of the ADC 112, the digital integrator 114, and the DC blocker filter 116 may be implemented in a processor. The processor may have an associated memory. The processor may be, for example and without limitation, a microprocessor, a microcontroller, or some other suitable processing device or circuitry, that interfaces with the memory or another suitable memory. The memory may be any of one or more of a variety of types of internal and/or external storage media such as, without limitation, RAM, ROM, EPROM(s), EEPROM(s), FLASH, and the like that provide a storage register, i.e., a machine readable medium, for data storage such as in the fashion of an internal storage area of a computer, and can be volatile memory or nonvolatile memory. The memory may store one or more routines which, when executed by the processor, cause the processor to implement at least some of its functionality.

While specific embodiments of the disclosed concept have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the disclosed concept which is to be given the full breadth of the claims appended and any and all equivalents thereof. 

What is claimed is:
 1. A current sensing circuit for use with a Rogowski coil arranged around a conductor having a primary current, the current sensing circuit comprising: input terminals structured to receive an output voltage of the Rogowski coil; filtering elements structured to filter high frequency voltage from the output voltage and to output a filtered output voltage; an amplifier structured to receive the filtered output voltage and produce a differential voltage; an analog to digital converter structured to convert the differential voltage to a digital differential voltage signal; a digital integrator structured to receive the digital differential voltage signal, to implement a discrete-time transfer function that is a transform of a transfer function of an analog integrator, and to output a digital integrator output signal; a direct current blocker filter structured to remove a direct current bias from the digital integrator output signal and to output a digital current output signal that is proportional to the primary current in the conductor.
 2. The current sensing circuit of claim 1, wherein the discrete-time transform implemented by the digital integrator is an impulse-invariant transform of the transfer function of the analog integrator.
 3. The current sensing circuit of claim 2, wherein the analog integrator is an RC-filter having a resistance of R and a capacitance of C; and wherein the discrete-time transfer function of the digital integrator is defined by the following equation: ${H(z)} = {\frac{y(z)}{x(z)} = {\frac{\alpha \cdot T_{S}}{1 - {e^{{- \alpha}\; T_{S}}z^{- 1}}} = \frac{b_{0}}{1 - {a_{1}z^{- 1}}}}}$ where T_(S) is a sampling interval; ${\alpha = \frac{1}{RC}};{a_{1} = {e^{{- \alpha}\; T_{S}} = e^{- \frac{T_{S}}{RC}}}};{b_{0} = {\alpha \cdot T_{S}}};$ and z⁻¹ denotes a one-sample delay.
 4. The current sensing circuit of claim 3, wherein the digital integrator has coefficients of a₁ and b₀; wherein a₁ is defined by the following equation: $a_{1} = \frac{\cos \left( {\Delta \; {n \cdot \omega_{e}}} \right)}{\cos \left\lbrack {\left( {{\Delta \; n} - 1} \right) \cdot \omega_{e}} \right\rbrack}$ wherein b₀ is defined by the following equation: b ₀=√{square root over (1−2a ₁ cos ω_(e) +a ₁ ²)} wherein Δn is a phase difference number of samples; ${\omega_{e} = {2\pi \frac{f_{e}}{f_{s}}}},$ f_(e) is a rated supply frequency, and f_(s) is a sampling frequency of the analog to digital converter.
 5. The current sensing circuit of claim 1, wherein the discrete-time transform implemented by the digital integrator is a bilinear transform of the transfer function of the analog integrator.
 6. The current sensing circuit of claim 5, wherein the analog integrator is an RC-filter having a resistance of R and a capacitance of C; and wherein the discrete-time transfer function of the digital integrator is defined by the following equation: ${H(z)} = {\frac{y(z)}{x(z)} = {\frac{\frac{\alpha \; T_{s}}{2 + {\alpha \; T_{s}}} + {\frac{\alpha \; T_{s}}{2 + {\alpha \; T_{s}}}z^{- 1}}}{1 - {\frac{2 - {\alpha \; T_{s}}}{2 + {\alpha \; T_{s}}}Z^{- 1}}} = \frac{b_{0} + {b_{1}z^{- 1}}}{1 - {a_{1}z^{- 1}}}}}$ where T_(S) is a sampling interval; ${{\alpha = \frac{1}{RC}};{a_{1} = \frac{2 - {\alpha \; T_{s}}}{2 + {\alpha \; T_{s}}}}},{b_{0} = {b_{1} = \frac{\alpha \; T_{s}}{2 + {\alpha \; T_{s}}}}},$ and z⁻¹ denotes a one-sample delay.
 7. The current sensing circuit of claim 6, wherein the digital integrator has coefficients of a₁, b₀, and b₁; wherein a₁ is defined by the following equation: $a_{1} = \frac{\cos \left\lbrack {\left( {{\Delta \; n} + \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}{\cos \left\lbrack {\left( {{\Delta \; n} - \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}$ and wherein b0 and b1 are defined by the following equation: $b_{0} = {b_{1} = \sqrt{\frac{1 - {2a_{1}\mspace{14mu} \cos \mspace{14mu} \omega_{e}} + a_{1}^{2}}{2 \cdot \left( {1 + {\cos \mspace{14mu} \omega_{e}}} \right)}}}$ wherein Δn is a phase difference number of samples; ${\omega_{e} = {2\pi \frac{f_{e}}{f_{s}}}},$ f_(e) is a rated supply frequency, and f_(s) is a sampling frequency of the analog to digital converter.
 8. The current sensing circuit of claim 1, wherein the direct current blocker filter has a transfer function defined by the following equation: ${H(z)} = {\frac{y(z)}{x(z)} = \frac{b_{0} + {b_{1}z^{- 1}}}{1 - {a_{1}z^{- 1}}}}$ where 0<a₁<1, b₀=1, and b₁=−1.
 9. The current sensing circuit of claim 1, wherein at least one of the digital integrator and the direct current blocker filter are implemented with a digital biquadratic filter having a transfer function defined by the following equation: ${H(z)} = {\frac{y(z)}{x(z)} = \frac{b_{0} + {b_{1}z^{- 1}} + {b_{2}z^{- 2}}}{1 - {a_{1}z^{- 1}} - {a_{2}z^{- 2}}}}$ where z⁻¹ denotes a one sample delay, z⁻² denotes a two sample delay, and a₁, a₂, b₀, b₁, and b₂ are coefficients.
 10. The current sensing circuit of claim 9, wherein the digital integrator is implemented with the digital biquadratic filter; wherein the discrete-time transform implemented by the digital integrator is an impulse-invariant transform of the transfer function of the analog integrator; and wherein a₁≠0, a₂=0, b₀≠0, b₁=0, and b₂=0.
 11. The current sensing circuit of claim 9, wherein the digital integrator is implemented with the digital biquadratic filter; wherein the discrete-time transform implemented by the digital integrator is a bilinear transform of the transfer function of the analog integrator; and wherein a₁≠0, a₂=0, b₀≠0, b₁=0, and b₂=0.
 12. The current sensing circuit of claim 9, wherein the direct current blocker filter is implemented with the digital biquadratic filter; and wherein a₁≠0, a₂=0, b₀=1, b₁=−1, and b₂=0.
 13. The current sensing circuit of claim 1, wherein the filtering elements include at least one ferrite bead.
 14. A method of implementing a digital integrator, the method comprising: providing a sampling frequency f_(s); providing a rated supply frequency f_(e); providing a phase difference number of samples Δn; obtaining a power grid's normalized angular frequency at rated condition using the following equation: $\omega_{e} = {2\pi \frac{f_{e}}{f_{S}}}$ obtaining a first coefficient a₁ based on the following equation: $a_{1} = \frac{\cos \left( {\Delta \; {n \cdot \omega_{e}}} \right)}{\cos \left\lbrack {\left( {{\Delta \; n} - 1} \right) \cdot \omega_{e}} \right\rbrack}$ obtaining a second coefficient based on the following equation: b ₀=√{square root over (1−2a ₁ cos ω_(e) +a ₁ ²)} implementing the digital integrator as a digital filter using the first coefficient a₁ and the second coefficient b₀.
 15. The method of claim 14, further comprising: scaling the second coefficient b₀ to obtain a scaled second coefficient b′₀; and implementing the digital integrator using the scaled second coefficient b′₀.
 16. The method of claim 14, wherein the digital integrator is an impulse invariant transform of an analog integrator.
 17. The method of claim 14, wherein implementing the digital integrator further comprises implementing the digital integrator in a current sensing circuit for sensing a primary current in a conductor based on a voltage output of a Rogowski coil arranged around the conductor.
 18. A method of implementing a digital integrator, the method comprising: providing a sampling frequency f_(s); providing a rated supply frequency f_(e); providing a phase difference number of samples Δn; obtaining a power grid's normalized angular frequency at rated condition using the following equation: $\omega_{e} = {2\pi \frac{f_{e}}{f_{S}}}$ obtaining a first coefficient a₁ based on the following equation: $a_{1} = \frac{\cos \left\lbrack {\left( {{\Delta \; n} + \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}{\cos \left\lbrack {\left( {{\Delta \; n} - \frac{1}{2}} \right) \cdot \omega_{e}} \right\rbrack}$ obtaining a second coefficient b₀ and a third coefficient b₁ based on the following equation: $b_{0} = {b_{1} = \sqrt{\frac{1 - {2a_{1}\mspace{14mu} \cos \mspace{14mu} \omega_{e}} + a_{1}^{2}}{2 \cdot \left( {1 + {\cos \mspace{14mu} \omega_{e}}} \right)}}}$ implementing the digital integrator as a digital filter using the first coefficient a₁, the second coefficient b₀, and the third coefficient b₁.
 19. The method of claim 18, further comprising: scaling the second coefficient b₀ to obtain a scaled second coefficient b′₀; scaling the third coefficient b₁ to obtain a scaled third coefficient b′₁; and implementing the digital integrator using the scaled second coefficient b′₀ and the scaled third coefficient b′₁.
 20. The method of claim 18, wherein the digital integrator is a bilinear transform of an analog integrator.
 21. The method of claim 18, wherein implementing the digital integrator further comprises implementing the digital integrator in a current sensing circuit for sensing a primary current in a conductor based on a voltage output of a Rogowski coil arranged around the conductor. 